1. Field of the Invention
The present invention relates to serialization of data, and, more particularly, to serialization with out using a clock.
2. Background Information
In many applications computer data is generated with the bits of a byte (herein byte refers to a group of two or more bits) available in parallel. The next bytes then follow in a time sequence. This may be referred to as bit parallel, byte serial. However, in many applications, a cable with parallel wires carrying the parallel bits is physically inconvenient, more susceptible to noise, and sending the bits in parallel may dissipate more power. In these applications the bits may be sent one at a time.
Known serializers use a clock synchronized to the data bits so a deserializer/receiver may reliably “clock in” (receive) the data bits. The clock must be reliable and is often generated by a PLL (phase locked loop). Other clocks circuit may be employed, for example, a ring of inverters may be arranged with positive feedback to oscillate. In each case these clocks require time to become usable. PLL's may take microseconds to “lock” and other clocks may take hundreds of nanoseconds to stabilize.
In the prior art, the data bits may be sent in bursts of one, two or a few bytes at a time with periodic times when nothing is being sent. In such an instance, if the clock is stopped to conserve power, the locking or stabilizing times must be repeated for each burst. Such prior art systems suffer time and/or power dissipation limitations.
One representative prior art example is found in U.S. Pat. No. 6,614,371 owned by Broadcom Corp, Irving Calif., USA. This patent discloses a two path data storage arrangement with select and delay logic for serializing data. The circuitry, however, uses a clock.
The present invention addresses the limitations found in the prior art by eliminating the clock. Therefore, the present invention incurs no time or power dissipation penalties while providing timing signals for reliable reception.